Adaptive edge-rate boosting driver with programmable strength for signal conditioning

ABSTRACT

A signal conditioner that includes a transition-detection module and a current-injection module. The transition-detection module is configured to receive a pair of differential signals from a data line and generate one or more comparator output signals and a transition-indication signal to indicate whether a transition has been detected on the differential signals. The current-injection module is configured to receive the comparator output signals and transition-indication signal from the transition-detection module, and generate appropriate currents for injection into the data line to boost edge rates of the differential signals when the transition-detection module detects a transition of the differential signals or remain high impedance when no transition occurs on the differential signals.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to U.S. Provisional Patent Application No. 62/007,681, filed on Jun. 4, 2014, titled “ADAPTIVE EDGE-RATE BOOSTING DRIVER WITH PROGRAMMABLE STRENGTH FOR SIGNAL CONDITIONING APPLICATIONS,” which is hereby incorporated herein by reference in its entirety.

BACKGROUND

Data transmission systems such as Universal Serial Bus (USB) 2.0 may benefit from signal conditioning to strengthen deteriorated signals due to transmission losses. Generally, a signal conditioner may comprise a receiver, an equalizer, and a transmitter. Such a signal conditioner often is uni-directional and is connected in series in data lines. That is, signals can flow in only one direction through the equalizer. For half-duplex or full-duplex data transmission, two signal conditioners are required, one for each of the two transmission channels that have opposite directions of data flow. This configuration often results in high circuit complexity and low power efficiency. For USB 2.0 system, this configuration will not be functional since the system configuration protocol cannot be understood and the communication between the host and device will be interrupted.

SUMMARY

The problems noted above are solved in large part by direction-agnostic signal conditioning systems and methods. In some embodiments, a signal conditioner may include a transition-detection module and a current-injection module. The transition-detection module is configured to receive a pair of differential signals from a data line and generate one or more comparator output signals and a transition-indication signal to indicate whether a transition has been detected on the differential signals. The current-injection module is configured to receive the comparator output signals and transition-indication signal from the transition-detection module, and generate currents for injection into the data line when the transition-detection module detects a transition of the differential signals or remain high impedance when no transition occurs on the differential signals.

Another illustrative embodiment is a method that includes receiving a pair of differential signals from a data line, by a transition-detection module. The method also includes generating a comparator output signal and a transition-indication signal to indicate whether a transition has been detected on the differential signals, by the transition-detection module. The method also includes generating a first pair of gating signals based on the comparator output signal from the transition-detection module for a first push-pull driver. The method also includes generating a second pair of gating signals based on the comparator output signal from the transition-detection module for a second push-pull driver. The method also includes generating a third gating signal based on the transition-indication signal from the transition-detection module for a first and a second blocking switches. The first blocking switch may be coupled between output of the first push-pull driver and one differential signal, and the second blocking switch may be coupled between output of the second push-pull driver and the other differential signal. The method also includes generating currents for injection into the data line to boost edge rates of the differential signals, through the first and second push-pull drivers and the first and second blocking switches, when the transition of the differential signals is detected.

Yes another illustrative embodiment is a system that include a first and a second differential comparators, an AND gate, a first and a second push-pull drivers, and a first and a second blocking switches. The first and second differential comparators are coupled in parallel with opposite input polarities and configured to receive a pair of differential signals from a data line and generate a first and a second comparator output signals, respectively. The AND gate is configured to receive the first and second comparator output signals and generate a transition-indication signal. The first and second comparator output signals and the transition-indication signal indicate whether a transition has been detected on the differential signals. The first blocking switch is coupled between output of the first push-pull driver and one differential signal. The second blocking switch is coupled between output of the second push-pull driver and the other differential signal. The first and second comparator output signals are regulated to generate a first pair of gating signals for the first push-pull driver, by a first AC-coupled pull-up RC network with a first inverting buffer and a first AC-coupled pull-down RC network with a first buffer. The first and second comparator output signals are regulated to generate a second pair of gating signals for the second push-pull driver, by a second AC-coupled pull-up RC network with a second inverting buffer and a second AC-coupled pull-down RC network with a second buffer. A third gating signal is generated for the first and second blocking switches, based on the transition-indication signal. The first and second push-pull drivers generate currents for injection into the data line, through the first and second blocking switches respectively, to boost edge rates of the differential signals when the transition of the differential signals is detected. The first and second blocking switches remain off to maintain high impedance when no transition occurs on the differential signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of an illustrative data transmission system in accordance with various embodiments;

FIG. 2 shows a block diagram of an illustrative signal conditioner in accordance with various embodiments;

FIG. 3 shows a circuit diagram of an illustrative transition-detection module in accordance with various embodiments;

FIG. 4 shows a circuit diagram of an illustrative current-injection module in accordance with various embodiments;

FIG. 5 shows exemplary signal waveforms of an illustrative signal conditioner in accordance with various embodiments; and

FIG. 6 shows a flow diagram of a method for conditioning signals in accordance with various embodiments.

NOTATION AND NOMENCLATURE

Certain terms are used through the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. The recitation “based on” is intended to mean “based at least in part on.” Therefore, if X is based on Y, X may be based on Y and any number of other factors.

DETAILED DESCRIPTION

The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

Data transmission is the physical transfer of data over a communication channel. For example, USB (e.g., USB 2.0) may transfer a pair of differential signals through data lines. A signal conditioner may be employed to strengthen deteriorated signals along the transmission path due to transmission losses. Generally, signal conditioners have been employed that include a receiver, an equalizer, and a transmitter. The equalizer provides the primary signal conditioning functionality, and the receiver and transmitter provide interfaces with the data lines. Such signal conditioners typically are connected in series in data lines. That is, the transmitted signal from an input/output (I/O) port is received by the signal conditioner, conditioned, and then retransmitted to the corresponding other I/O port. Signals can flow in only one direction from the receiver to the transmitter through the equalizer. The signal conditioner is therefore uni-directional. For half-duplex or full-duplex data transmission where bidirectional data transfer is required, two signal conditioners will be employed, one for each of the two transmission channels. This configuration often results in high circuit complexity and low power efficiency. For USB 2.0 system, this configuration will not be functional since the system configuration protocol cannot be understood and the communication between the host and device will be interrupted.

To mitigate these limitations, in an embodiment a direction-agnostic signal conditioner may be employed which may tap into data lines in a parallel connection, rather than breaking up the data lines and being connected in series between the I/O ports. The disclosed signal conditioner may include a transition-detection module and a current-injection module. The transition-detection module is configured to receive differential signals from the data lines and generate one or more comparator output signals and a transition-indication signal. When a transition of the differential signals on the data lines occurs, i.e., the two signals change from one logic state to another state, the comparator output signals and the transition-indication signal may transition from one logic state to another state as well. Thus, the state changes of the comparator output signals and the transition-indication signal may serve as a detection of differential signal transitions.

The signal conditioner's current-injection module is configured to receive the comparator output signals and the transition-indication signal from the transition-detection module and generate appropriate injection currents. The injection currents are injected into the differential data lines to strengthen the differential signals. In one example, if a transition of the differential signals is detected, the current-injection module generates currents for injection into the data lines to boost edge rates of the differential signals. A positive current may be injected into the differential signal with a rising edge and a negative current may be injected into the other differential signal with a falling edge. If the differential signals have no transition, e.g., the differential signals are in steady states, the current-injection module may remain high impedance to maintain signal DC level.

This signal conditioner described herein is direction-agnostic which means it conditions the signals on the data lines regardless of which direction the data signals are flowing. Signals may be transferred in both directions over the data lines while the signal conditioner is being employed and thus two signal conditions (one for each data signal direction) are not necessary. For half-duplex or full-duplex data transmission, only one signal conditioner may be needed.

FIG. 1 shows a block diagram of an illustrative data transmission system 100 in accordance with various embodiments. A pair of differential signals D_(P) and D_(M) is transferred over data lines 104 and 105 between two I/O ports 101 and 102. Each I/O port 101 and 102 may include a receiver, a transmitter, or a transceiver (both transmitter and receiver) to send or receive data signals to the corresponding other I/O port. The I/O ports may be coupled together via, for example, a USB cable and may be capable of simplex or duplex data transmissions. An example of such a data transmission system is a peripheral device coupled to the USB port of a computer via a USB cable.

A signal conditioner 103 taps into the data lines 104 and 105 in a parallel connection and receives the differential signals D_(P) and D_(M) via wires 106 and 107. The signal conditioner 103 may detect transitions of the differential signals D_(P) and D_(M) and inject currents to boost the signal edge rates during each such detected transition. For example, if the differential signal D_(P) changes from HIGH to LOW and the other differential signal D_(M) changes from LOW to HIGH, a negative current is injected into the data line 104 via the wire 106 and a positive current is injected into the data line 105 via the wire 107, by the signal conditioner 103. If the differential signal D_(P) changes from LOW to HIGH and the other differential signal D_(M) changes from HIGH to LOW, a positive current is injected into the data line 104 via the wire 106 and a negative current is injected into the data line 105 via the wire 107, by the signal conditioner 103

FIG. 2 shows a block diagram of an illustrative signal conditioner 103 in accordance with various embodiments. The signal conditioner 103 in this example may include a transition-detection module 201 and a current-injection module 202. The transition-detection module 201 receives the differential signals D_(P) and D_(M) via the wires 106 and 107 and generates a transition-indication signal 204 and one or more comparator output signal 205, to indicate a transition has been detected on the differential signals D_(P) and D_(M). The current-injection module 202 is configured to receive the transition-indication signal 204 and the comparator output signal 205 from the transition-detection module 201, and determines whether positive or negative currents are to be injected into each differential signal based on the detection of transitions by the transition-detection module 202. The current-injection module 202 generates appropriate injection currents 206 and 207 for each detected transition on the differential signals D_(P) and D_(M), or remains high impedance when D_(P) and D_(M) have no transitions.

FIG. 3 shows a circuit diagram of an illustrative transition-detection module 201 in accordance with various embodiments. The transition-detection module 201 may include two differential comparators 301 a and 301 b and an AND gate 302. The two differential comparators 301 a and 301 b are coupled in parallel with opposite input polarities. As such, the differential signal D_(M) is provided to the positive (+) input of comparator 301 a and to the negative (−) input of comparator 301 b. Similarly, the other differential signal D_(P) is provided to the negative (−) input of comparator 301 a and to the positive (+) input of comparator 301 b. The differential comparators 301 a and 301 b receive the differential signals D_(P) and D_(M) and generate comparator output signals 205 a and 205 b, respectively. The AND gate 302 is configured to receive the comparator output signals 205 a and 205 b and generate a transition-indication signal 204 to indicate whether a transition has been detected on the differential signals D_(P) and D_(M).

The differential comparators 301 a and 301 b may each be a differential receiver with a relatively low propagation delay, which compares the difference between its positive input and its negative input to a non-zero threshold voltage (V_(th)). When the difference between the positive input and the negative input is equal to or higher than V_(th), the differential comparators 301 a and 301 b generate logic high output signals 205 a and 205 b, respectively. Otherwise, the differential comparators 301 a and 301 b generate logic low output signals 205 a and 205 b, respectively. For example,

-   -   If (D_(M)−D_(P))≧V_(th), 205 a is HIGH; Otherwise, 205 a is LOW;         and     -   If (D_(P)−D_(M))≧V_(th), 205 b is HIGH; Otherwise, 205 b is LOW.         Early detection of a transition on the differential signals can         be obtained because the differential comparators 301 a and 301 b         have the non-zero threshold voltage (V_(th)). Further, the         threshold V_(th) may be adjustable to allow the differential         comparators 301 a and 301 b to interface with a variety of data         transmission protocols with different signal voltages. The         transition-indication signal 204 depends on the comparator         output signals 205 a and 205 b. The transition-indication signal         204 is HIGH when both of the comparator output signals 205 a and         205 b are HIGH. The transition-indication signal 204 is LOW when         one of the comparator output signals 205 and 205 b is LOW.

The transition-indication signal 204 and comparator output signals 205 a and 205 b change states in correspondence to transitions of the differential signals D_(P) and D_(M). Thus, they may serve as a detection of differential signal transitions. For example, at one instant, the differential signals D_(P) and D_(M) are in steady states where D_(P) is HIGH and D_(M) is LOW. The difference between the positive input and the negative input of 301 a, (D_(M)−D_(P)), is at its minimum and thus the comparator output signal 205 a is LOW. The difference between the positive input and the negative input of 301 b, (D_(P)−D_(M)), is at its maximum and thus the comparator output signal 205 b is HIGH. The output of the AND gate 302, i.e., the transition-indication signal 204, is therefore LOW. If a transition occurs where D_(P) transitions from HIGH to LOW and D_(M) transitions from LOW to HIGH, the comparator output signal 205 a will change from LOW to HIGH and the comparator output signal 205 b will change from HIGH to LOW. Because the differential comparators 301 a and 301 b have the non-zero threshold voltage V_(th), the comparator output signals 205 a and 205 b change states either earlier (with a rising edge) or later (with a falling edge) than the zero-crossing of the differential signals D_(P) and D_(M). For example, the rising edge of 205 a will occur near beginning of the transition once (D_(P)−D_(M)) becomes less than V_(th). The falling edge of 205 b will occur near end of the transition when (D_(M)−D_(P)) becomes larger than V_(th). Consequently, the transition-indication signal 204 will change from LOW to HIGH with the rising edge of 205 a near beginning of the transition, and will change from HIGH back to LOW with the falling edge of 205 b near end of the transition. In other words, the transition-indication signal 204 remains HIGH during this transition of the differential signals.

Similarly, if at another instant, the differential signals D_(P) and D_(M) are at steady states where D_(P) is LOW and D_(M) is HIGH, the comparator output signal 205 a is HIGH, the comparator output signal 205 b is LOW, and the transition-indication signal 204 is LOW. If a transition occurs where D_(P) transitions from LOW to HIGH and D_(M) transitions from HIGH to LOW, the comparator output signal 205 a will change from HIGH to LOW and the comparator output signal 205 b will change from LOW to HIGH. Further, the rising edge of 205 b will occur near beginning of the transition and the falling edge of 205 a will occur near end of the transition. Consequently, the transition-indication signal 204 will change from LOW to HIGH with the rising edge of 205 b near beginning of the transition, and will change from HIGH back to LOW with the falling edge of 205 a near end of the transition. Again, the transition-indication signal 204 remains HIGH during the transition of the differential signals D_(P) and D_(M). In summary, the transition-indication signal 204 is HIGH during transitions of the differential signals D_(P) and D_(M), and remains LOW otherwise.

FIG. 4 shows a circuit diagram of an illustrative current-injection module 202 in accordance with various embodiments. The current-injection module 202 may include two push-pull drivers 401 a and 401 b, which may be further coupled to output blocking switches 420 a and 420 b, respectively. Each of the push-pull drivers 401 a and 401 b is driven by a pair of gating signals. Push-pull driver 401 a is driven by gating signal pair 440 a and 441 a, while push-pull driver 401 is driven by gating signal pair 440 b and 441 b. The two blocking switches 420 a and 420 b are driven by a gating signal 442. The two push-pull drivers 401 a and 401 b, together with associated blocking switches 420 a and 420 b, work similarly. To facilitate understanding, the operating principle of the push-pull driver 401 a and its blocking switch 420 a is first described below.

The push-pull driver 401 a may include a p-channel MOSFET (pMOS) 402 a coupled in series with an n-channel MOSFET (nMOS) 403 a between a supply voltage (V_(cc)) and ground. The pMOS 402 a turns on when the gating signal 440 a is equal to or lower than its threshold voltage (V_(p) _(—) _(th)) and turns off when the gating signal 440 a is higher than V_(p) _(—) _(th). The gating signal 440 a is generated based on regulating the comparator output signal 205 a. The comparator output signal 205 a is regulated by a first inverting buffer 430 and a first AC-coupled pull-up resistor-capacitor (RC) network 410. The inverting buffer 430 may be employed to match polarity of the comparator output signal 205 a with required polarity of the gating signal 440 a. The AC-coupled pull-up RC network 410 may include a capacitor 414, a plurality of resistors 412, and a plurality of switches 413. The capacitor 414 is coupled in series with the gate of the pMOS 402 a. The resistors 412, in series with and selected by the switches 413, are coupled in parallel between a voltage source (V_(P) _(—) _(bias)) and the gate of the pMOS 402 a.

Depending on the status of the comparator output signal 205 a, the pMOS 402 a may operate in different modes. For example, if the comparator output signal 205 a is in a steady state (i.e., at a constant DC voltage), the AC-coupled pull-up RC network 410 blocks the comparator output signal 205 a via the capacitor 414 regardless of whether 205 a is HIGH or LOW. Instead, the AC-coupled pull-up RC network 410 clamps the gating signal 440 a at a stable voltage higher than V_(p) _(—) _(th) through the resistors 412 and the voltage source V_(p) _(—) _(bias). Thus, the pMOS 402 a remains off. However, upon occurrence of a falling edge of the comparator output signal 205 a, the transient voltage of 205 a will cause a transient voltage on the gating signal 440 a to the gate of pMOS 402 a. The gating signal 440 a will transition with a voltage spike, from the clamping voltage first to a higher voltage and then back to the clamping voltage. Throughout the transient response to the falling edge of signal 205 a, the gating signal 440 a will remain higher than V_(p) _(—) _(th) and therefore the pMOS 402 a still remains off. Finally, if there is a rising edge of the comparator output signal 205 a, the transient voltage of 205 a will cause the gating signal 440 a to transition with a voltage sag, from the clamping voltage first to a voltage lower than V_(p) _(—) _(th) and then back to the clamping voltage. Correspondingly, the pMOS 402 a will first turn on and then turn off. In short, the pMOS 402 a turns on when there is a rising edge of the comparator output signal 205 a and remains off otherwise.

The first AC-coupled pull-up RC network 410 provides an RC time constant. The time constant of the first AC-coupled pull-up RC network 410 may be configured by changing its resistance through control of the switches 413. By controlling the time constant, the AC-coupled pull-up RC network 410 may control the length of time and magnitude of the transient voltage of the gating signal 440 a and thus the duration and strength of the pMOS 402 a to remain ON.

The nMOS 403 a operates in an opposite way, meaning that the nMOS 403 a turns on when the gating signal 441 a is equal to or higher than its threshold voltage (V_(n) _(—) _(th)) and turns off when the gating signal 441 a is lower than V_(n) _(—) _(th). The gating signal 441 a is generated based on regulating the comparator output signal 205 b. The comparator output signal 205 b is regulated by a first buffer 431 and a first AC-coupled pull-down RC network 411. The buffer 431 may be employed to compensate for delays and synchronize the gating signal 441 a with the other gating signals. The AC-coupled pull-down RC network 411 may include a capacitor 417, a plurality of resistors 415, and a plurality of switches 416. The capacitor 417 is coupled in series with the gate of the nMOS 403 a. The resistors 415, in series with and selected by the switches 416, are coupled in parallel between a voltage source (V_(n) _(—) _(bias)) and the gate of the nMOS 403 a.

Depending on the status of the comparator output signal 205 b, the nMOS 403 a may operate in different modes. For example, if the comparator output signal 205 b is in a steady state (i.e., at a constant DC voltage), the AC-coupled pull-down RC network 411 blocks the comparator output signal 205 b via the capacitor 417 regardless of whether 205 b is HIGH or LOW. Instead, the AC-coupled pull-down RC network 411 clamps the gating signal 441 a at a stable voltage lower than V_(n) _(—) _(th) through the resistors 415 and the voltage source V_(n) _(—) _(bias). Thus, the nMOS 403 a remains off. However, upon occurrence of a falling edge of the comparator output signal 205 b, the transient voltage of 205 b will cause a transient voltage on the gating signal 441 a to the gate of nMOS 403 a. The gating signal 441 a will transition with a voltage sag, from the clamping voltage first to a lower voltage and then back to the clamping voltage. Throughout the transient response to the falling edge of signal 205 b, the gating signal 441 a will remain lower than V_(n) _(—) _(th) and therefore nMOS 402 a still remains off. Finally, if there is a rising edge of the comparator output signal 205 b, the transient voltage of 205 b will cause the gating signal 441 a to transition with a voltage spike, from the clamping voltage first to a voltage higher than V_(n) _(—) _(th) and then back to the clamping voltage. Correspondingly, the nMOS 403 a will first turn on and then turn off. In short, the nMOS 403 a turns on when there is a rising edge of the comparator output signal 205 b and remains off otherwise.

The first AC-coupled pull-down RC network 441 provides an RC time constant. The time constant of the first AC-coupled pull-down RC network 411 may be configured by changing its resistance through control of switches 416. By controlling the time constant, the AC-coupled pull-down RC network 411 may control the length of the time and magnitude of the transient voltage of the gating signal 441 a and thus the duration and strength of the nMOS 403 a to remain ON. The switches can be set (on or off) during a configuration process by control logic (not shown).

The blocking switch 420 a is coupled to the output of the push-pull driver 401 a and generates an output 207 that is fed back into the differential signal D_(M). The blocking switch 420 a may be implemented by an nMOS driven by the gating signal 442. The gating signal 442 is generated based on the transient-indication signal 204. A third buffer 432 may be employed to compensate for delays and synchronize the gating signal 442 with the other gating signals. The blocking switch 420 a turns on when the gating signal 442 is equal to or higher than its threshold voltage, and remains off (i.e., in high impedance) otherwise.

As mentioned above, the push-pull driver 401 b with the blocking switches 420 b works similarly to the push-pull driver 401 a with the blocking switches 420 a. The push-pull driver 401 b may be configured similarly as the push-pull driver 401 a, including a pMOS 402 b coupled in series with an nMOS 403 b between the supply voltage (V_(cc)) and ground. The pMOS 402 b and nMOS 403 b are driven by the gating signals 440 b and 441 b, respectively.

The gating signal 440 b to the pMOS 402 b is generated based on regulating the comparator output signal 205 b. The comparator output signal 205 b is regulated by a second inverting buffer 430 and a second AC-coupled pull-up RC network 410. The second inverting buffer 430 may be employed to match polarity of the comparator output signal 205 b with required polarity of the gating signal 440 b. The second AC-coupled pull-up RC network 410 may include a capacitor 414, a plurality of resistors 412, and a plurality of switches 413. The capacitor 414 is coupled in series with the gate of the pMOS 402 b. The resistors 412, in series with and selected by the switches 413, are coupled in parallel between the voltage source (V_(p) _(—) _(bias)) and the gate of the pMOS 402 b. In reference to the operating principle of the push-pull driver 401 a and its blocking switch 420 a, the pMOS 402 b may operate in different modes depending on the status of the signal 205 b. For example, if the comparator output signal 205 b is in a steady state (i.e., at a constant DC voltage), the pMOS 402 b remains off because its gating signal 440 b is clamped at a stable voltage higher than its threshold voltage (V_(p) _(—) _(th)) through the resistors 412 and the voltage source (V_(p) _(—) _(bias)). Upon occurrence of a falling edge of the comparator output signal 205 b, the transient voltage of 205 b will cause a transient voltage spike on the gating signal 440 b. The pMOS 402 b still remains off since the gating signal 440 b remains higher than V_(p) _(—) _(th) throughout the transient. Finally, if there is a rising edge of the comparator output signal 205 b, the transient voltage of 205 b will cause the gating signal 440 b to transition with a voltage sag from the clamping voltage first to a voltage lower than V_(p) _(—) _(th) and then back to the clamping voltage. Thus, the pMOS 402 b will first turn on and then turn off. In short, the pMOS 402 b turns on when there is a rising edge of the comparator output signal 205 b and remains off otherwise.

The gating signal 441 b to the nMOS 403 b is generated based on regulating the comparator output signal 205 a. The comparator output signal 205 a is regulated by a second buffer 431 and a second AC-coupled pull-down RC network 411. The second buffer 431 may be employed to compensate for delays and synchronize the gating signal 441 b with the other gating signals. The second AC-coupled pull-down RC network 411 may include a capacitor 417, a plurality of resistors 415, and a plurality of switches 416. The capacitor 417 is coupled in series with the gate of the nMOS 403 b. The resistors 415, in series with and selected by the switches 416, are coupled in parallel between the voltage source (V_(n) _(—) _(bias)) and the gate of the nMOS 403 a. Depending on the status of the comparator output signal 205 a, the nMOS 403 b may operate in different modes. For example, if the comparator output signal 205 a is in a steady state (i.e., at a constant DC voltage), the nMOS 403 b remains off because its gating signal 441 b is clamped at a stable voltage lower than its threshold voltage (V_(n) _(—) _(th)) through the resistors 415 and the voltage source (V_(n) _(—) _(bias)). Upon occurrence of a falling edge of the comparator output signal 205 a, the transient voltage of 205 a will cause a transient voltage sag on the gating signal 441 b. The nMOS 403 b still remains off since the gating signal 441 b remains lower than V_(n) _(—) _(th) throughout the transient. Finally, if there is a rising edge of the comparator output signal 205 a, the transient voltage of 205 a will cause the gating signal 441 b to transition with a voltage spike, from the clamping voltage first to a voltage higher than V_(n) _(—) _(th) and then back to the clamping voltage. Thus, the nMOS 403 b will first turn on and then turn off. In short, the nMOS 403 b turns on when there is a rising edge of the comparator output signal 205 a and remains off otherwise.

The time constant of the second AC-coupled pull-up RC network 410 may be configured by changing its resistance through control of the switches 413. By controlling the time constant, the second AC-coupled pull-up RC network 410 may control the length of time and magnitude of the transient voltage of the gating signal 440 b and thus the duration and strength of the pMOS 402 b to remain ON. The time constant of the second AC-coupled pull-down RC network 411 may be configured by changing its resistance through control of switches 416. By controlling the time constant, the second AC-coupled pull-down RC network 411 may control the length of the time and magnitude of the transient voltage of the gating signal 441 b and thus the duration and strength of the nMOS 403 b to remain ON.

The blocking switch 420 b is coupled to the output of the push-pull driver 401 b and generates an output 206 that is fed back into the differential signal D_(P). The blocking switch 420 b may be implemented by an nMOS driven by the gating signal 442. The blocking switch 420 b turns on when the gating signal 442 is equal to or higher than its threshold voltage, and remains off (i.e., in high impedance) otherwise.

Referring now to FIG. 5, the waveforms of the various signals described above will be further explained. As shown herein, at the beginning, the differential signals D_(P) and D_(M) are in steady states where D_(P) is HIGH and D_(M) is LOW. The comparator output signal 205 a from differential comparator 301 a is LOW, the comparator output signal 205 b from differential comparator 301 b is HIGH, and the transition-indication signal 204 from the AND gate 302 is LOW. The gating signal 442, which is based on the signal 204 with a small delay from the buffer 432, is LOW as well. Thus, the blocking switches 420 a and 420 b remain off, which causes the signal conditioner 103 to remain high impedance.

Next, a transition occurs where the differential signal D_(P) transitions from HIGH to LOW and the other differential signal D_(M) transitions from LOW to HIGH. The comparator output signal 205 a changes the state from LOW to HIGH and the comparator output signal 205 b changes the states from HIGH to LOW. The rising edge of 205 a occurs near beginning of the transition and the falling edge of 205 b occurs near end of the transition. Between the rising edge of 205 a and falling edge of 205 b, both comparator output signals are HIGH and thus the transition-indication signal 204 is HIGH. Further, the rising edge of the comparator output signal 205 a causes a voltage sag on the gating signal 440 a to the pMOS 402 a and causes a voltage spike on the gating signal 441 b to the nMOS 403 b, which turn on the pMOS 402 a and nMOS 403 b respectively. The gating signal 442, following the signal 204 with a delay, becomes HIGH during the transition, which turns on the two blocking switches 420 a and 420 b. Thus, a positive current 207 is injected into the differential signal D_(M) from the power supply V_(cc) through the pMOS 402 a and blocking switch 420 a, and a negative current 206 returns from the other differential signal D_(P) and back to ground through the blocking switch 420 b and nMOS 403 b. The rising edge of D_(M) and falling edge of D_(P) are boosted by the positive current 207 and negative current 206, respectively.

Further, it is noted that the length of the time when the signals 204 and 442 are high is adaptive (i.e., inversely proportional) to the edge rates of the differential signals D_(P) and D_(M). Lower edge rates of D_(P) and D_(M) cause a slower transition and a longer period of time for the signals 204 and 442 to remain HIGH (and thus the two blocking switches 420 a and 420 b to remain ON). Higher edge rates of D_(P) and D_(M) cause a faster transition and a shorter period of time for the signals 204 and 442 to remain HIGH (and thus the two blocking switches 420 a and 420 b to remain ON). Therefore, the length of time of the current injections during the transition is adaptive (i.e., inversely proportional) to the edge rates of the differential signals D_(P) and D_(M).

When the differential signals D_(P) and D_(M) get into next steady states where D_(P) is LOW and D_(M) is HIGH, the comparator output signal 205 a from differential comparator 301 a is HIGH, the comparator output signal 205 b from differential comparator 301 b is LOW, and the transition-indication signal 204 from the AND gate 302 is LOW. The gating signal 442, following the signal 204 with a delay, is LOW as well. Thus, the blocking switches 420 a and 420 b remain off, which causes the signal conditioner 103 to remain high impedance.

Finally, another transition occurs where the differential signal D_(P) transitions from LOW to HIGH and the other differential signal D_(M) transitions from HIGH to LOW. The comparator output signal 205 b changes the state with a rising edge near the beginning of the transition, and the comparator output signal 205 a changes the state with a falling edge near the end of the transition. Between the rising edge of 205 b and falling edge of 205 a, both comparator output signals are HIGH and thus the transition-indication signal 204 is HIGH. The rising edge of the comparator output signal 205 b causes a voltage sag on the gating signal 440 b to the pMOS 402 b and causes a voltage spike on the gating signal 441 a to the nMOS 403 a, which turn on the pMOS 402 b and nMOS 403 a respectively. Further, the gating signal 442, following the signal 204 with a delay, becomes HIGH during the transition, which turns on the two blocking switches 420 a and 420 b. Thus, a positive current 206 is injected into the differential signal D_(P) from the power supply V_(cc) through the pMOS 402 b and blocking switch 420 b, and a negative current 207 returns from the other differential signal D_(M) and back to ground through the blocking switch 420 a and nMOS 403 a. The rising edge of D_(P) and falling edge of D_(M) are boosted by the positive current 206 and negative current 207, respectively. Again, the length of time of the current injections during the transition is adaptive (i.e., inversely proportional) to the edge rates of the differential signals D_(P) and D_(M).

The differential signals D_(P) and D_(M) go through cycles of above steady states and transitions along with the transfer of data packets. The signal conditioner 103 shifts between the high-impedance state and current-injection mode accordingly. When D_(P) and D_(M) are in steady states, the signal conditioner 103 remains high impedance. Whenever a transition occurs on the differential signals, the signal conditioner 103 generates appropriate injection currents to boost the edge rates of D_(P) and D_(M).

FIG. 6 shows a flow diagram of a method 600 for conditioning a pair of differential signals D_(P) and D_(M) in accordance with various embodiments. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some embodiments may perform some of the actions shown, or additional actions. In some embodiments, at least some of the operations of the method 600, as well as other operations described herein, can be performed by signal conditioner 103 including transition-detection module 201 and current-injection module 202, and implemented by an integrated circuit (IC) executing instructions stored in a non-transitory computer readable storage medium.

The method begins in block 602 with receiving pair of differential signals D_(P) and D_(M) from data lines 104 and 105. In an embodiment, the differential signals D_(P) and D_(M) are received by the transition-detection module 201. The transition-detection module 201 may include two differential comparators 301 a and 301 b coupled in parallel with opposite input polarities, and AND gate 302.

In block 604, the method 600 continues with generating comparator output signal 205. In an embodiment, the differential comparators 301 and 302 a are configured to receive the differential signals D_(P) and D_(M), and generate the comparator output signals 205 a and 205 b respectively. The signals 205 a and 205 b are generated by comparing the difference between the positive input and the negative input to the threshold voltage (V_(th)), by the comparators 301 and 302. When the difference between the positive input and the negative input is equal to or higher than V_(th), the comparator output signals 205 a and 205 b are HIGH. Otherwise, the comparator output signals 205 a and 205 b are LOW.

In block 606, the method 600 continues with generating transition-indication signal 204. In an embodiment, the AND gate 302 is configured to receive the comparator output signals 205 a and 205 b and generate the transition-indication signal 204. The transition-indication signal 204 is HIGH when both of the comparator output signals 205 a and 205 b are HIGH. The transition-indication signal 204 is LOW when one of the comparator output signals 205 and 205 b is LOW.

In block 608, the method 600 continues with indicating whether a transition has been detected on the differential signals D_(P) and D_(M), based on the comparator output signal 205 and transition-indication signal 204. In one embodiment, when there is a transition of the differential signals D_(P) and D_(M), the comparator output signals 205 a and 205 b will change states accordingly and the transition-indication signal 204 will change to HIGH during the transition. Thus, the state changes of the comparator output signal and the logic high state of the transition-indication signal may serve as a detection of transitions on the differential signals.

In block 610, the method 600 continues with generating a first pair of gating signals 440 a and 441 a based on the comparator output signal 205 for a first push-pull driver 401 a. In one embodiment, the first push-pull driver 401 a includes a pMOS 402 a in series with an nMOS 403 a between a supply voltage V_(cc) and ground. The gating signals 440 a to the pMOS 402 a is generated based on regulating the comparator output signal 205 a by a first inverting buffer 430 and a first AC-coupled pull-up RC network 410. The gating signals 441 a to the nMOS 403 a is generated based on regulating the comparator output signal 205 b by a first buffer 431 and a first AC-coupled pull-down RC network 411.

In block 612, the method 600 continues with generating a second pair of gating signals 440 b and 441 b based on the comparator output signal 205 for a second push-pull driver 401 b. In one embodiment, the second push-pull driver 401 b includes a pMOS 402 b in series with an nMOS 403 b between the supply voltage V_(cc) and ground. The gating signals 440 b to the pMOS 402 b is generated based on regulating the comparator output signal 205 b by a second inverting buffer 430 and a second AC-coupled pull-up RC network 410. The gating signals 441 b to the nMOS 403 b is generated based on regulating the comparator output signal 205 a by a second buffer 431 and a second AC-coupled pull-down RC network 411.

In block 614, the method 600 continues with generating a third gating signal 442 for the first and second blocking switches 420 a and 420 b. In an embodiment, the third gating signal 442 is generated based on the transition-indication signal 204 with a delay compensation by a third buffer 432.

In block 616, the method of 600 continues with generating injection currents 206 and 207 to boost edge rates of the differential signals D_(P) and D_(M) when a transition of the differential signals is detected. In one embodiment, the first blocking switch 420 a is coupled to output of the first push-pull driver 401 a and generates output 207 that is fed back into the differential signal D_(M). The second blocking switch 420 b is coupled to output of the second push-pull driver 401 b and generates output 206 that is fed back into the differential signal D_(P). When the differential signal D_(P) transitions from HIGH to LOW and the other differential signal D_(M) transitions from LOW to HIGH, the third gating signal 442, based on the transition-indication signal 204, causes the first and second blocking switches 420 a and 420 b to turn on. The comparator output signal 205 a transitions with a rising edge, causing a voltage sag on the gating signal 440 a to the pMOS 402 a and a voltage spike on the gating signal 441 b to the nMOS 403 b, which turn on the pMOS 402 a and nMOS 403 b respectively. Thus, a positive current 207 is injected into the differential signal D_(M) from the power supply V_(cc) through the pMOS 402 a and first blocking switch 420 a, and a negative current 206 returns from the other differential signal D_(P) and back to ground through the second blocking switch 420 b and nMOS 403 b. The rising edge of D_(M) and falling edge of D_(P) are boosted by the positive current 207 and negative current 206, respectively. When the differential signal D_(P) transitions from LOW to HIGH and the other differential signal D_(M) transitions from HIGH to LOW, the third gating signal 442, based on the transition-indication signal 204, causes the first and second blocking switches 420 a and 420 b to turn on. The comparator output signal 205 b transitions with a rising edge, causing a voltage sag on the gating signal 440 b to the pMOS 402 b and a voltage spike on the gating signal 441 a to the nMOS 403 a, which turn on the nMOS 403 a and pMOS 402 b respectively. Thus, a positive current 206 is injected into the differential signal D_(P) from the power supply V_(cc) through the pMOS 402 b and second blocking switch 420 b, and a negative current 207 returns from the other differential signal D_(M) and back to ground through the first blocking switch 420 a and nMOS 403 a. The rising edge of D_(P) and falling edge of D_(M) are boosted by the positive current 206 and negative current 207, respectively. When the differential signals D_(P) and D_(M) are in steady states without a transition, the transition-indication signal 204 is in a logic low state, and thus the two blocking switches 420 a and 420 b remain off in high impedance with minimum power consumptions.

The signal conditioner and method described herein are direction-agnostic, since they condition data signals by boosting their edge rates through current injections during transitions regardless of which direction the data signals are flowing. Signals may be transferred in both directions over data lines while such a signal conditioner is being employed. For half-duplex or full-duplex data transmission, only one signal conditioner may be needed. The signal conditioner may tap into data lines in a parallel connection without breaking up the data lines. The signal conditioner has relatively high power efficiency since it conditions signals only during transitions and remain high impedance otherwise. The duration of the current injections is adaptive (i.e., inversely proportional) to the edge rates of the differential signals, important to avoid over-shoots in signal conditioning that can causes further signal distortions. Finally, the signal conditioner may work with a variety of data transmission protocols with different signal voltages, by adjusting the threshold voltage of differential comparators of the transition-detection module.

The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications. 

What is claimed is:
 1. A signal conditioner, comprising: an transition-detection module configured to receive a pair of differential signals from a data line and generate a transition-indication signal and a comparator output signal to indicate whether a transition has been detected on the differential signals; and a current-injection module configured to receive the transition-indication signal and the comparator output signal from the transition-detection module, and generate currents for injection into the data line to boost edge rates of the differential signals when the transition of the differential signals is detected or remain high impedance when the differential signals have no transition.
 2. The signal conditioner of claim 1, wherein the comparator output signal comprises first and second comparator output signals, and wherein the transition-detection module comprises: first and second differential comparators coupled in parallel with opposite input polarities, the differential comparators configured to receive the differential signals and generate the first and second comparator output signals respectively; and an AND gate configured to receive the first and second comparator output signals and generate the transition-indication signal; wherein the first and second comparators and the AND gate cause the comparator output signals and the transition-indication signal, respectively, to change state as a result of transitions of the differential signals to indicate whether the transition has been detected on the differential signals.
 3. The signal conditioner of claim 2, wherein each of the first and the second differential comparators comprises a differential receiver with an adjustable threshold voltage.
 4. The signal conditioner of claim 1, wherein the current-injection module comprises: a first push-pull driver configured to receive a first pair of gating signals; a second push-pull driver configured to receive a second pair of gating signals; a first blocking switch coupled between output of the first push-pull driver and one differential signal, the first blocking switch configured to receive a third gating signal; a second blocking switch coupled between output of the second push-pull driver and the other differential signal, the second blocking switch configured to receive the third gating signal; wherein the first and second pairs of gating signals are generated based on regulation of the comparator output signal of the transition-detection module; wherein the third gating signal is generated based on the transition-indication signal of the transition-detection module; wherein the first and second push-pull drivers are configured to generate currents for injection through the first and second blocking switches into the data line to boost edge rates of the differential signals when the transition of the differential signals is detected; and wherein the first and second blocking switches remain high impedance when no transition occurs on the differential signals.
 5. The signal conditioner of claim 4, wherein each of the first and second blocking switches comprises an n-channel MOSFET.
 6. The signal conditioner of claim 4, wherein each of the first and second push-pull drivers comprises a p-channel MOSFET in series with an n-channel MOSFET between a supply voltage and ground.
 7. The signal conditioner of claim 6, wherein the gating signal for the p-channel MOSFET of the first push-pull driver is generated based on regulation of the comparator output signal from the transition-detection module by a first AC-coupled pull-up RC network and a first inverting buffer, and the gating signal for the p-channel MOSFET of the second push-pull driver is generated based on regulation of the comparator output signal from the transition-detection module by a second AC-coupled pull-up RC network and a second inverting buffer.
 8. The signal conditioner of claim 6, wherein the gating signal for the n-channel MOSFET of the first push-pull driver is generated based on regulation of the comparator output signal from the transition-detection module by a first AC-coupled pull-down RC network and a first buffer, and the gating signal for the n-channel MOSFET of the second push-pull driver is generated based on regulation of the comparator output signal from the transition-detection module by a second AC-coupled pull-down RC network and a second buffer.
 9. The signal conditioner of claim 7, wherein each of the first and second AC-coupled pull-up RC networks comprises: a capacitor; a plurality of resistors; and a plurality of switches; wherein, for each of the AC-coupled pull-up RC networks, the capacitor is coupled in series with the gate of the p-channel MOSEFT of the push-pull driver; and wherein each of the resistors is in series with and selected by a corresponding one of the switches and, wherein the series combinations of resistors and switches are coupled in parallel between a voltage source and the gate of the p-channel MOSEFT of the push-pull driver.
 10. The signal conditioner of claim 8, wherein each of the first and the second AC-coupled pull-down RC networks comprises: a capacitor; a plurality of resistors; and a plurality of switches; wherein, for each of the AC-coupled pull-down RC networks, the capacitor is coupled in series with the gate of the n-channel MOSEFT of the push-pull driver; and wherein each of the resistors is in series with and selected by a corresponding one of the switches, and wherein the series combinations of resistors and switches are coupled in parallel between a voltage source and the gate of the n-channel MOSEFT of the push-pull driver.
 11. The signal conditioner of claim 9, wherein time constants of the first and second AC-coupled pull-up RC networks are configurable through selective control of the plurality of switches.
 12. The signal conditioner of claim 10, wherein the time constants of the first and second AC-coupled pull-down RC networks are configurable, respectively, by changing the resistance of the RC network through control of the switches.
 13. A method, comprising: generating a comparator output signal and a transition-indication signal to indicate whether a transition has been detected on a pair of differential signals on a data line; generating a first pair of gating signals for a first push-pull driver, based on regulating the comparator output signal; generating a second pair of gating signals for a second push-pull driver, based on regulating the comparator output signal; generating a third gating signal for first and second blocking switches, based on the transition-indication signal; and based on detection of the transition of the differential signals, controlling the first and second block switches to thereby generate currents for injection into the data line to boost edge rates of the differential signals through the first and second push-pull drivers and the first and second blocking switches.
 14. The method in claim 13, further comprising: receiving the pair of differential signals at inputs of each of first and second differential comparators, the first differential comparator receiving the differential signals in an opposite polarity as is received by the second differential comparator; and logically AND'ing outputs of the first and second comparators to generate the transition-indication signal.
 15. The method of claim 13, further comprising: regulating the comparator output signal by a plurality of AC-coupled pull-up RC networks and a plurality of AC-coupled pull-down RC networks to generate the first and second pairs of gating signals for the push-pull drivers.
 16. The method of claim 13, further comprising: generating currents for injection into the data line only during transitions of the differential signals and maintaining the first and second blocking switches in high impedance when no transitions occur on the differential signals.
 17. A system, comprising: a plurality of differential comparators coupled in parallel with opposite input polarities, the differential comparators are configured to receive a pair of differential signals from a data line and generate a comparator output signals; a logic gate configured to conjoin the comparator output signals and generate a transition-indication signal; a plurality of push-pull drivers configured to receive gating signals; and a plurality of blocking switches coupled between the push-pull drivers and at least one of the differential signals; wherein differential comparators and the logic gate are configured to cause the comparator output signals and the transition-indication signal, respectively, to change states in correspondence to transitions of the differential signals to indicate whether the transition has been detected on the differential signals; wherein the push-pull drivers are configured to inject currents into the data line, through the blocking switches, to boost edge rates of the differential signals based on detection of the transition of the differential signals; and wherein the blocking switches are configured to remain high impedance when no transition occurs on the differential signals.
 18. The system of claim 17, wherein the push-pull drivers each comprises a p-channel MOSFET in series with an n-channel MOSFET between a supply voltage and ground; wherein the gating signals for the push-pull drivers are generated based on regulation of the comparator output signals by a plurality of AC-coupled pull-up RC networks and a plurality of AC-coupled pull-down RC networks; wherein the blocking switches each comprises an n-channel MOSFET; and wherein the gating signal for the blocking switches is generated based on the transition-indication signal.
 19. The system of claim 18, the AC-coupled pull-up RC networks each comprises: a capacitor; a plurality of resistors; and a plurality of switches; wherein the capacitor is coupled in series with the gate of the p-channel MOSEFT of the push-pull driver; and wherein the plurality of resistors, in series with and selected by the plurality of switches, are coupled in parallel between a voltage source and the gate of the p-channel MOSEFT of the push-pull driver.
 20. The system of claim 18, wherein the AC-coupled pull-down RC networks each comprises: a capacitor; a plurality of resistors; and a plurality of switches; wherein the capacitor is coupled in series with the gate of the n-channel MOSEFT of the push-pull driver; and wherein the plurality of resistors, in series with and selected by the plurality of switches, are coupled in parallel between a voltage source and the gate of the n-channel MOSEFT of the push-pull driver. 